Design Verification (UVM) - Canada #20846

  • Toronto, Canada

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional design verification engineer to join our interface IP team in Toronto. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.  

  

As a design verification engineer, the candidate will be reporting to digital engineering director and is a Full-Time position. The team is working on the next generation multi-protocol SERDES Phy IP. The design verification engineer will have full ownership over the IP verification planning and execution and will be expected to interact extensively with digital, analog and system engineers in the team.  

 

Location: in-office (hybrid) Toronto, Canada preferred; other Canada remote locations available.

Responsibilities

Responsibilities: 

  • Composing detailed verification plans while working closely with the digital design and system teams 
  • Developing randomly constrained and automated UVM or similar test environments for RTL and GL DUTs with multi voltage and clock domains and incorporating analog and mixed signal behavioral models and 3rd party IPs 
  • Developing test cases to match algorithm model and/or mixed signal model for the SERDES IP  
  • Running coverage regressions to meet the defined coverage goals 
  • Tracking and communicating verification status, issues, and concerns 
  • Interact with application team and customers on bring-up issues, firmware development and design integration. 

Qualifications

 Requirements: 

  • Candidate should possess a Bachelor or Master degree in EE/CS/related discipline.  
  • Proven industry experience in developing testing environments from scratch using SV and UVM methodology is a must. 
  • 10+ years of  experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies. 
  • Hand-on experience with modern IC design CAD tools and environment 
  • Familiarity with code quality metrics. 
  • Excellent analytical and problem-solving skills along with attention to details. 
  • Time Management skill, good communication and documentation skills.  

Preferred Experience: 

  • Experience with one of the following will be considered as asset: Verification of clock and data recovery circuits, signal processing verification, analog/mixed signal IP modeling and verification  
  • C/ C++, Perl, Python and MATLAB programming and scripting abilities are highly preferred 

 

About Rambus 

With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future.  

Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program and gym membership. 

   
Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.  

  

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may let us know in the application. 

 

For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/

 

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