Lead MTS DFT

  • Bangalore, India

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead DFT Engineer to join our Interface IP Cores DFT team team in Bengaluru. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

 

As Lead DFT Engineer, the candidate will be responsible for design, implementation, and verification of all aspects of DFT on complex IPs and test chips at advanced process technology nodes viz. 5nm/7nm/10nm/14nm supporting multiple fabs.

Responsibilities

As a DFT engineer, you will be responsible for:

  • Complete DFT ownership of projects including:
    • Test architecture definition for testchip and IP
    • Identifying and implementing RTL changes for DFT
    • Performing scan insertion
    • Developing timing constraints for test mode timing closure
    • Scan and ATPG for different fault models
    • Boundary scan, ACJTAG, IEEE 1500 implementation and verification
    • IEEE1687 (iJTAG) for functional manufacturing tests
    • Running zero delay and timing simulations and debugging on all the above aspects
    • Supporting post silicon bring up
    • Interacting with customers on DFT aspects and support Marketing & Pre-Sales team
    • You may be working on very high speed and low power designs
  • This role requires close interaction with multiple cross functional teams across geographies to align on project receivables/deliverables.
  • Mentoring junior engineers and participate in innovation/automation

Qualifications

  • B.E./B.Tech/M.E/M.Tech with 8-10 years of relevant work experience and strong understanding of DFT concepts and good communication skills
  • Strong hands-on experience using industry standard EDA Tools is must e.g. Mentor Tessent, Cadence Modus, Synopsys TestMAX
  • Experience with logic simulators from one or more EDA vendors
  • Experience with RTL lint tools like Synopsys Spyglass
  • Experience in scan insertion, coverage analysis and debugging skills on faults coverage enhancement is must
  • Exposure to RTL2GDS flow and tasks such as Logic design, RTL implementation & verification, synthesis and scan insertion, writing test mode SDC, STA, Logic Equivalent Checking must
  • Programming in Perl/Tcl/Python or other scripting languages is desired
  • Experiences in post silicon validation, debug and support on ATE are desired
  • Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability is a plus

Rambus offers an extremely competitive compensation package, which includes a strong base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program and gym membership.

 

Rambus creates cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting. Our chips, customizable IP cores, architecture licenses, tools, services, training and innovations improve the competitive advantage of our customers. We collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation labs. Our products are integrated into tens of billions of devices and systems, powering and securing diverse applications, including Big Data, Internet of Things (IoT), mobile, consumer and media platforms. At Rambus, we are makers of better. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.

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