Lead Layout Design Engineer

  • Agoura Hills, United States

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Digital Design Engineer to join our Buffer Chip Design team in Agoura Hills, California. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

 

As a Lead Layout Engineer, the candidate will be reporting to the Technical Director, Engineering and is a Full-Time position.

Responsibilities

Layout Lead of high-speed Digital/Analog chips

  • Planning: Top level floor-planning, sub-module partitioning, power-grid and delegating
  • Implementation: Follow the latest decks from the foundaries such as TSMC/SMIC etc
  • Verification: Complete checks using the Foundary decks all the way to Tapeout, record violations and work with design for waivers if any
  • Interact with design leads to come up with the best solutions

Qualifications

Qualificaton

  • Bachelor's or Master's Degree in Electrical or Computer Engineering
  • 7+ years of relevant digital/ASIC/IC design experience
  • Significant Experience with multiple IC designs
  • Significant Experience with standard ASIC software tools (Cadence-Virtuoso)
  • Successful past digital leadership roles
  • Self-starter and fast learner with excellent interpersonal skills
  • Knowledge of Analog block layout for better matching such as common centroid layouts and dummy structures etc.

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About Rambus

With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future.

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