Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead Engineer to join our IP Engineering PHY/Logic Design team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

As a Lead Engineer, which is a Full-Time position, you will integrate PCIe sub-system. Sub-system will have pre-dominantly PCIe compliant PHY and controller. Sub-system may contain various other IPs as well based on use case. It will also contain IP specific glue logic as IPs on sub-system come from various IP providers.

Responsibilities

• Be a technical digital design lead for sub-system
• Own the design and work with cross functional teams (IP designers, verification, physical design, timing) for execution of sub-system
• Interact and participate in discussion with customers on IP integration, reviews
• Over the period grow expertise on various PCIe PHY and controllers
• Debug simulations independently over the period w/o help from actual IP designers and make correct decisions
• Guide verification team on verification plan and code coverage
• RTL quality checks – Lint, CDC, synthesis readiness
• Own the delivery schedule, articulate the progress, highlight bottlenecks and get resolution from cross functional teams spread over Geo’s

Qualifications

• Master’s degree or Bachelor’s degree in Electronics or Electrical Engineering
• 8+ years of relevant work experience in micro-architecture, RTL design, synthesis and STA including SDC development
• Driving design flows and overall methodology
• Experience in working independently and leading large complex module design

Preferred qualifications:

• Experience in the design of digital logic and components in RTL, building/own the top-level integration as well as in synthesis, timing closure, and power-optimization of digital designs
• Experience in coding with Verilog and/or System Verilog along with scripting languages such as Perl, Tcl, or Python
• Hands on experience on Lint/CDC, SDC ownership and qualification, Timing ECO iterations, debugging in mixed-signal simulation environment, etc.
• Experience in cross functional interaction with verification, DFT and physical design teams
• Understanding of PCIe protocol including good knowledge on PCS and PIPE i/f

About Rambus

With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future.

Rambus offers a competitive compensation package including base salary, bonus, equity, employee stock purchase plan, comprehensive medical and dental benefits, time-off program and gym membership.

Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.

For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.