At Rambus, we are turning incredible possibilities into everyday reality by helping to deliver the innovations that greatly impact the world we live in. We create leading-edge semiconductor and IP products, spanning memory and interfaces to security to smart sensors. Our products are integrated into tens of billions of devices and systems around the globe, running critical applications for Big Data, Internet of Things (IoT), mobile, consumer and media platforms.

And our history runs deep – we have been in Silicon Valley for 25+ years and are continually anticipating key technology trends and are developing innovations that drive market changes. From a pure IP provider to becoming a fabless chipmaker, Rambus is evolving to address critical challenges in the semiconductor industry.

As a dynamic organization, we are always seeking to hire exceptional talent to join some of the brightest inventors and engineers in the world to explore their passions to develop products that have real life impact. As well, Rambus benefits are among the most comprehensive and competitive.

Responsibilities

• Responsible for Co-simulation of mix signal IPs of SERDES and Memory PHY.
• Developing behavioral models of mixed signal designs at various abstraction levels for use in functional verification.
• Correlating model and schematic behavior with circuit developer
• Developing a generic modeling framework in System Verilog that can be reused for various designs
• Documenting functionality of model, it’s architecture and use cases
• Should be able to handle a small team technically including aligning deliverables to meet project schedule

Qualifications

• Master’s in electrical/Electronic/CS Engineering with relevant experiences of 8+ yrs or Bachelor’s with 10+ yrs
• Expert in co-simulation methodology and toolset including experience with Cadence Virtouso
• Deep understanding of highspeed analog/mixed-signal design concepts.  Able to understand and debug the circuits and logic behavior/issues.
• Working knowledge of high-speed Analog & DSP based Serdes/Memory systems
• Knowledge on CDR, equalization, and adaptation algorithms for PHY
• Experience with Verilog/SystemVerilog, Matlab/Simulink, C and Python
• Domain knowledge of at least one of the protocols – DDR3/4, PCIe Gen1-6, Ethernet KR, JESD, CPRI etc.
• Clear communication and presentation skills.
• Good to have -  
• Knowledge of C++, System-C, Verilog-A, Hspice/Spectre Spice languages, and modeling Virtual Platforms
• DSP concepts
• Experience with Keysight ADS or QCD

Rambus offers a competitive compensation package, which includes a strong base salary, bonus, equity, employee stock purchase plan, comprehensive medical benefits, time-off program and gym membership.

Rambus creates cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting. Our chips, customizable IP cores, architecture licenses, tools, services, training and innovations improve the competitive advantage of our customers. We collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation labs. Our products are integrated into tens of billions of devices and systems, powering and securing diverse applications, including Big Data, Internet of Things (IoT), mobile, consumer and media platforms. At Rambus, we are makers of better. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.