SMTS Logic Design

  • Bangalore, India

Rambus, a best-in-class chip, and silicon IP provider, is seeking to hire a hardworking, driven, and intellectually curious Logic Design Engineer to join our IP Engineering PHY/Logic Design team in Bangalore, to deliver premium quality high-speed interface IPs. Candidate will be joining some of the brightest inventors and engineers in the world, to develop products that make data faster and safer. We are responsible for delivering groundbreaking custom high speed interface PHY blocks in SoC/ Controller designs. Our team is involved in designing logic blocks of PHY IPs in advance nodes like 7nm, 10nm, 14nm etc. that adds additional challenges which can be embraced highly.

As a Senior Member of Technical Staff (SMTS) - Logic Design, which is a Full-Time position, you will be contributing micro-architecture derived from top level architecture specification & design RTL of various digital blocks of the interface IPs, model & contribute to the top-level integration of macros. You will also develop from different models of complex circuits and integrate them

Responsibilities

As a SMTS logic design engineer in the PHY logic team, you will

  • Help contribute in micro-architecture, design RTL, debug, trace, and be active member of delivering next gen high speed interface physical layer IP’s like DDR5/4/3, HBM3/2E/2, GDDR6, Serdes 28G/32G/56G/64G/112G in advance nodes like 5nm, 7nm, 14nm etc.
  • Be responsible for the logic design/ RTL coding and timing closure of multiple blocks in high performance custom integrated circuit environment
  • Develop various analog macro models and integrate to enable high coverage, and drive the methodology on mixed signal IP flows on modelling, simulations, and timing closure
  • Collaborate with verification team to ensure implementation meets both architectural and micro-architectural intent
  • Participate in running quality checks such as Lint, clock domain crossing etc.
  • Collaborate with physical design, design for test, co-simulation & timing teams to optimize tradeoffs within the design

Qualifications

  • Master’s degree or bachelor’s degree in Electronics or Electrical Engineering
  • 5+ years of relevant work experience in RTL design, Synthesis, and timing closure
  • Substantial background in debugging designs as well as simulation environment
  • Driving mixed-signal design flows and improve different methodologies.
  • Experience in delivering high-speed, high-performance IP design blocks & integrating them in advanced technology nodes
  • Deep understanding of fundamental digital design concepts

 

Preferred qualifications:

  • Experience in the design of digital circuits and components in RTL, building/lead the top-level integration as well as in synthesis, timing closure, and power-optimization of digital designs.
  • Experience coding within Verilog and/or System Verilog along with scripting languages such as Perl, Tcl, or Python.
  • Hands on experience on Lint/CDC, SDC ownership and qualification, Timing ECO iterations, debugging in mixed-signal simulation environment, etc.
  • Experience in multi-functional interaction with verification, DFT and physical design teams.
  • Understanding of the mixed signal IP flow with modelling and simulation. 

About Rambus

With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future.

Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program and gym membership.

  
Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.

 

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