MTS,DFT Engineering

Bangalore | India

At Rambus, we are turning incredible possibilities into everyday reality by helping to deliver the innovations that greatly impact the world we live in. We create leading-edge semiconductor and IP products, spanning memory and interfaces to security to smart sensors. Our products are integrated into tens of billions of devices and systems around the globe, running critical applications for Big Data, Internet of Things (IoT), mobile, consumer and media platforms.

 

And our history runs deep – we have been in Silicon Valley for 25+ years and are continually anticipating key technology trends and are developing innovations that drive market changes. From a pure IP provider to becoming a fabless chipmaker, Rambus is evolving to address critical challenges in the semiconductor industry.

 

As a dynamic organization, we are always seeking to hire exceptional talent to join some of the brightest inventors and engineers in the world to explore their passions to develop products that have real life impact. As well, Rambus benefits are among the most comprehensive and competitive in Silicon Valley.

Responsibilities

  • As a DFT engineer at Rambus, you will be responsible for Design, Implementation and verification of LBIST, MBIST, PBIST, SCAN, ATPG, Boundary Scan, P1500, IO BIST, JTAG etc. on complex chips at advanced process technology nodes viz. 65nm/40/28nm/14nm etc.
  • Experience in SCAN insertion, Coverage analysis, debugging skills on faults, and enhancement is required.
  • You will be working on high speed and very low power designs.
  • Also involved in design and development of At-speed testing, complex DFT mode definitions, STA and Silicon bring up process.

Qualifications

  • UG- in DFT & RTL2GDS flow domain/ DFT covering the following aspects.
  • Strong hands on Experience using Standard EDA Tools –. Experience with logic simulators from one or more EDA vendor. Experience on Mentor Fastscan, Cadence’s encounter test, Tessent tools desired.
  • Reasonably good exposure in RTL2GDS flow tasks such as Synthesis, implementation, STA and IR drop
  • Strong understanding & hands on experience with industry standard DFT techniques such as boundary scan, Memory BIST, BISA and BIRA, Scan/ on-chip-Compression/ ATPG/ At-speed Fault simulation and Logic BIST and BIST for high speed serial links.
  • Post Silicon Validation, ATE Debug and Support are needed.
  • Very good understanding of the complete Logic design, Modeling, RTL-Implementation & Verification, Logic Synthesis, Logic Equivalent Checking & Static Timing Analysis.
  • Experience in fault grading, timing verification analog behavioral model validation and test vector delivery conversion flow desired.
  • Experience working with multiple complex chips at different technologies like 65nm/40/28nm etc
  • Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability
  • Programming in Perl and Tcl is a plus.

 

Rambus offers an extremely competitive compensation package, which includes a strong base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program and gym membership.

 

Rambus creates cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting. Our chips, customizable IP cores, architecture licenses, tools, services, training and innovations improve the competitive advantage of our customers. We collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation labs. Our products are integrated into tens of billions of devices and systems, powering and securing diverse applications, including Big Data, Internet of Things (IoT), mobile, consumer and media platforms. At Rambus, we are makers of better. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.

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