Principal Analog Design Engineer - 20327

  • 4453 North First Street, Suite 100, Alviso, San Jose, California, United States, 95134

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Analog Design Engineer to join our Bufferchip Design team in San Jose, California. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

 

As a Principal Analog Design Engineer, the candidate will be reporting to the Manager of Analog Design Engineering and is a Full-Time position.

Responsibilities

• Have full ownership of Analog IP, its major blocks or sub blocks
• Define the architecture and uArchitecture of the IP’s and its sub functions
• Understand and disseminate applicable standards and its relevance in a given project to the team
• Responsible to develop and design the high speed circuit blocks used in Rambus
• Design, simulate and characterize high performance CMOS circuits (ADC, temp sensor, LDO, PLL circuits).
• The designer will be responsible for all aspects of designs such as schematic capture, layout review, simulation & analysis of critical electrical and timing parameters, documentation and silicon bring-up.
• Will be responsible to work with the system engineering team for Silicon bring up and Characterization.
• Mentoring of junior designers where applicable.

Qualifications

  • MS EE and 7+ years or PhD EE and 5+ years’ experience of CMOS analog/mixed-signal circuit design
  • The candidate should have prior experience of ADC, temp sensor, LDO and PLL circuit design. The senior position requires demonstrated ability to have worked in these domains and a sound understanding of the standards, protocols, practical aspects of circuit design in DSM process nodes (28nm, 16nm,14nm) are very desirable.
  • Strong and sound fundamental knowledge of basic building blocks (Ex: bias generation, on-chip regulation, on-chip impedance circuits and PLL) is essential.
  • Experience in designing memory interfaces such as DDR/3/4 and LP3/4 or serial links such as USB/XAUI/, CEI6/ LVDS /PCIE//SATA and Display Port etc.) is desirable.
  • Experience working in leading R&D and future technology development projects is desirable.
  • The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams.

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About Rambus

With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future.
Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program and gym membership.
Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.
Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may let us know in the application.
For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.

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