PE CAD Engineering

  • 4453 North First Street, Suite 100, Alviso, San Jose, California, United States, 95134

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Analog/Mixed-signal CAD Engineer to join our Buffer Chip Engineerging team in San Jose. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.  

  

As a Principal Analog/Mixed-signal CAD Engineer, the candidate will be reporting to Director CAD Engineering and is a Full Time position. 

Responsibilities

  • Drive and implement specific Custom Design Automation (CDA) flows such as 
  • Schematic entry, Layout design - color aware and DPT/MPT 
  • Parasitic Extraction for transistor level flow 
  • Device modelling and Simulation environment in Cadence ADE/ADE-XL/Assembler/Explorer 
  • Knowledge and hands-on experience in physical verification – DRC, LVS, DFM checks 
  • Knowledge of Deep Submicron Topics such as LFD, PM, MAS, Litho  etc. 
  • Knowledge of Electrical verification like IREM (VoltusFi/Totem), RelXpert, ERC, PERC 
  • Drive Interfacing between Digital and Analog/Mixed signal methodologies. 
  • Develop Custom flows automation, rule deck customizations, improve productivity and efficiency. 
  • Train, Deployment and support of CDA to Design teams. 
  • Debug flow issues and testcases from Design teams for Simulation, LVS, DRC, IREM, post layout simulation.  
  • Responsible for assisting Tapeouts, final chip finishing runs, interface across foundry/customer for rulesets etc. 

Qualifications

  • Good knowledge Analog/Mixed signal Design and Development in Cadence Virtuoso environment. 
  • Good knowledge on EDA Tools and Methodologies in Analog/Mixed Signal Design and Development. 
  • Good understanding of standards and formats like Spice, CDL, LEF, DEF, Verilog, SPEF, GDS, OA, .LIB, etc. 
  • Good knowledge on scripting skills – PERL, TCL, Skill, Ruby, C-Shell scripts etc. 
  • Good knowledge on Data management aspects using ICManage / Cliosoft / Perforce / Methodics / SVN etc. 
  • Good knowledge of 14nm/10nm/7nm finfet technologies 
  • Good knowledge of Deep Submicron Issues / technologies ( < 45 nm technology) 
  • Understanding of LSF cluster, Job submission and monitoring is a plus 
  • Understanding of tool License features and license administration is a plus  

 

About Rambus 

 

With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future.  

Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program and gym membership. 

   
Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.  

  

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may let us know in the application. 

 

For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/

 

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