PE DFT

  • Bangalore, India

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal DFT Engineer to join our IP Cores DFT team team in Bengaluru. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

 

As a Principal DFT Engineer, the candidate will be  responsible for design, implementation, and verification of all aspects of DFT on complex IPs and test chips at advanced process technology nodes viz. 5nm/7nm/10nm/14nm supporting multiple fabs.

Responsibilities

As a DFT engineer, you will be responsible for:

  • Complete DFT ownership of projects including:
    • Test architecture definition
    • Identifying and implementing RTL changes for DFT
    • Performing scan insertion
    • Developing timing constraints for test mode timing closure
    • Scan and ATPG for different fault models
    • Boundary scan, ACJTAG, IEEE 1500 implementation and verification
    • IEEE1687 (iJTAG) for functional manufacturing tests
    • Running zero delay and timing simulations and debugging on all the above aspects
    • Supporting post silicon bring up
    • Interacting with customers on DFT aspects and support Marketing & Pre-Sales team
    • You will be working on very high speed and low power designs.
  • This role requires close interaction with multiple cross functional teams across geographies to align on project receivables/deliverables.
  • Mentoring junior engineers and drive innovation/automation

Qualifications

  • E/B.Tech/M.E/M.Tech with 8-12 years of relevant work experience and strong understanding of DFT concepts and good communication skills
  • Strong hands-on experience using industry standard EDA Tools is must
  • Experience with logic simulators from one or more EDA vendors
  • Experience on Mentor Tessent tools and Cadence Modus Test tools
  • Experience with RTL lint tools like Synopsys Spyglass
  • Experience in scan insertion, coverage analysis and debugging skills on faults coverage enhancement is required
  • Programming in Perl/Tcl/Python or other scripting languages is desired
  • Experience in post silicon validation, ATE debug and support is desired
  • Exposure to RTL2GDS flow and tasks such as synthesis and scan insertion, STA and IR drop
  • Good understanding of Logic design, RTL implementation & verification, logic synthesis, Logic Equivalent Checking & Static Timing Analysis is a plus
  • Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability

 

 

About Rambus

With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future.

Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program and gym membership.

   

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may let us know in the application.

 

For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.

 

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