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Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional PE Principal DFT to join our CXL team in Canada. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.
The newly established Interconnect Business Unit is hiring a Principal DFT lead to architect, design, implement, verify, test and support all aspects of DFT on complex SoCs at advanced process technology nodes (14nm/10nm/7nm) using advanced DFT methodologies.
Position can be located in - San Jose, California; Raleigh, North Carolina, Vancouver, Canada, or other US / Canada or Banglore, India locations.
Proven expertise in Test architecture definition for complex multi-million gate SoCs
Strong understanding of DFT concepts and advanced methodologies
Proven hands-on SoC experience in:
Scan and ATPG for different fault models
MBIST insertion, implementation, and verification
Boundary scan, ACJTAG, IEEE 1500 implementation and verification
IEEE1687 (iJTAG) and fault grading for functional manufacturing tests
Logic BIST understanding and expertise
Exposure and understanding Loopback testing is a bonus
Strong experience in scan insertion, coverage analysis and debugging skills on faults coverage enhancement is required.
Developing constraints for scan-based logic insertion and test mode timing closure
Understanding zero delay and timing simulations and debugging on all the above aspects
Strong hands-on Experience using industry standard EDA Tools
Experience with logic simulators from one or more EDA vendors
Experience on Mentor Tessent tools and Cadence Modus Test tools
Experience with RTL lint tools like Synopsys Spyglass
Experience working on Low Power designs and Power-aware DFT.
Support post-silicon bring-up.
Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability
Identifying and implementing RTL changes for DFT
Good understanding of Logic design, RTL implementation & verification, logic synthesis, Logic Equivalent Checking & Static Timing Analysis is a plus
Exposure to RTL2GDS flow is a plus
Experience on multiple complex chips at different technologies like 14nm/10/7nm etc.
Good scripting skills in TCL, PERL/Python
Self-driven individuals with good collaborative skills Handling complete DFT ownership in projects.
Good verbal and written communication skills
Bachelor’s or Master’s degree in Electrical / Electronics Engineering from reputed institution.
10+ years post-qualification experience in DFT.
With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future.
Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits.
Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.
Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may let us know in the application.
For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.