PE,Logic Verification Engineering

Bangalore | India

Responsibilities

Duties:

  • Design, architect and implement testbench development and execution
  • Involve in architectural decisions with design team during development phase
  • Contribute in implementation of UVM based testbench and verif flow/automation scripts
  • Involve in Coverage analysis and identifying Test plan gaps
  • Provide Technical guidance to other members in the Verification team
  • Assist/Involve in FPGA/Emulation and understand h/w and s/w interface
  • Identify and improve system level throughput/bandwidth bottlenecks
  • Participate in post silicon validation

Qualifications

Skills/Qualifications:

  • Bachelor's/Master's degree in Electronics/Electrical Engineering
  • 8+ years of verification experience
  • Significant experience in HVL based verification with 2+ years expertise in SV & UVM
  • Good understanding of Serial protocols and PHY design/verification.
  • Ethernet and SOC/Product verification experience
  • Strong knowledge of PCIe Gen1/2/3/4 protocol
  • Experience with PCIe applications for enterprise/data center applications is a big plus
  • Prior experience in PCIe system level software/hardware post-silicon debug is a plus
  • Should have created Testbench architectures, as well as build verification setup from scratch to ensuring successful verification closure of reasonably complex designs
  • Should have knowledge on all aspects of verification components & verification closure
  • Should have flair for documentation, defining/improving methodology and achieving productivity improvement
  • Ability to provide technical guidance & resolving technical conflicts desired
  • Ability to communicate technical and project issues to business and technical senior management
  • MUST have very good verbal and written communication skills

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