PE Physical Design

  • Bangalore, India

 Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal engineer physical design to join our IP Cores  team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

 

As a Principal engineer physical design the candidate will have a higher exposure to the management and he/she will be part of major technical decision making. The role gives an opportunity to work on high speed designs in the range of 3.5Ghz. The design requires out of box thinking to meet tighter PPA.

Responsibilities

  • Lead complete ownership of Bufferchip SOC implementation.
  • Take complete ownership for Block and SOC implementation depending on the complexity.
    • Responsible for independent planning and execution of all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out  on 22nm nodes or below.
    • Must have participated in all stages of the design. (floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREM)
    • Well versed with the timing closure (STA), timing closure methodologies.
    • Should be able to provide clear directions to the team on PnR flows.
    • Role involves tasks in estimating power using industry standard tool , designing power grid , analyze power grid, doing static IR drop, dynamic IR drop
    • Role involves analyzing DRC, LVS,ERC and PERC rule files for industry standard layout verification
  • Good communication skill to negotiate with top level for convergence.
  • Work closely with Project leader for creating schedule, tracking and raising issues / risks to project management.
  • Participate in Mentoring new joiners in the group on technical skills.
  • Provide inputs for CAD/DA team from Design Implementation perspective.
  • Work closely with DFT team on scan aspects and provide inputs from physical design.
  • Continuously work on methodology and productivity improvements.

Qualifications

  • Must have minimum Bachelors degree in EE/ECE (degree’s related to electronics) from a reputed institute.
  • Must have at least 10+years of experience, out of which at least 5 years should be related to physical design at chip level / block level.
  • Must have implemented and completed a minimum of 8 design tapeouts.
  • Must have detailed knowledge of EDA tools and flows, Cadence related foundation flows and RTL2GDS flow is desired
  • Experience in Tcl/Tk, PERL is a Plus
  • Synthesis experience and exposure besides chip implementation flows is an added advantage

 

About Rambus

With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future.

Rambus offers a competitive compensation package including base salary, bonus, equity, employee stock purchase plan, comprehensive medical and dental benefits, time-off program and gym membership.

  
Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.

 

For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.

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