PE Physical Design

  • Bangalore, India

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal engineer physical design to join our Bufferchip team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

 

As a Principal engineer physical design the candidate will have a higher exposure to the management and he/she will be part of major technical decision making. The role gives an opportunity to work on high speed designs in the range of 3.5Ghz. The design requires out of box thinking to meet tighter PPA.

Responsibilities

  • Experience doing multi-mode multi-corner (MMMC) timing and power analysis using primetime/Tempus.
  • Experience in DMSA/Tweaker ECO flows for PPA improvements.
  • Experience in Hierarchical and Flat timing flow bring-up and timing analysis on interface paths. Block level/Fullchip/SOC level/Mixed signal timing path analysis and fixing.
  • Experience in manual timing fixes, ECO generation for MCMM mode corners. 
  • Good understanding of SDC constraints and able to translate timing requirements into constraints.
  • Experience with logic synthesis (preferably using Genus-LP/DCT), Physical Design and DFT logic insertion.
  • Experience in timing execution and convergence including setup, hold, burn-in, noise, timing budgeting and efficient timing closer for DDR/PCIe, SERDES, USB, Ethernet PHYs.  Work closely with design team to understand mixed signal design integration, QTM models generation and set the appropriate constraints in timing analysis flows and methodology.
  • Experience with low power methodologies and UPF/CPF constraints.
  • Experience in TCL, Perl scripting

Qualifications

  • Must have at least 10 – 12 years of experience, out of which at least 8 years should be related to STA/Synthesis .
  • Must have Involved in high Speed design tape-outs and constraint development across modes.
  • Must have detailed knowledge of EDA tools and flows, Cadence related foundation flows and RTL2GDS flow is desired
  • Experience in Tcl/Tk, PERL is a Plus

About Rambus

With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future.

 

Rambus offers a competitive compensation package including base salary, bonus, equity, employee stock purchase plan, comprehensive medical and dental benefits, time-off program and gym membership. 

 

Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.

 

For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.

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