PE Logic Design

  • Bangalore, India

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Engineering to join our IP Engineering PHY/Logic Design team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

As a Principal Engineer, which is a Full-Time position, you design the digital blocks of the IP and own the top-level integration of high-speed analog macro’s in Testchip/Controller/SOC environment. You will develop from lower level of circuit blocks modelling to macro level and then to top-level and own the IP’s functionality checks w.r.t specs.

Designing high-speed mixed signal PHY IP’s in advance nodes like 7nm, 10nm, 14nm etc. is adds additional complexity and challenges which you will learn and embrace during this job.

Responsibilities

  • Be a technical digital design lead for the PHY IP’s.
  • Be part of the high speed interface PHY IP logic team delivering DDR5/4/3, HBM3/2E/2, GDDR6, Serdes 28G/32G/56G/64G/112G in advance nodes like 5nm, 7nm, 14nm etc.
  • Own the design and work with cross functional teams (circuit, verification, PD, timing) for execution on multiple IP’s on multiple technology nodes
  • Interact and participate in discussion with customer on IP integration, reviews
  • Define or participate in micro-architecture definition and drive for power, performance and area (PPA) targets or enhancements
  • Drive the methodology on mixed signal IP flows on modelling, simulations, timing closure

Qualifications

  • Master’s degree or Bachelor’s degree in Electronics or Electrical Engineering
  • 8+ years of relevant work experience in micro-architecture, RTL design, synthesis and STA
  • Driving design flows and overall methodology.
  • Experience in leading projects to deliver high-speed, high-performance IP design over advance technology nodes
  • Experience in leading both IP design and TestChip/SoC integration.

Preferred qualifications:

  • Experience in the design of digital circuits and components in RTL, building/own the top-level integration as well as in synthesis, timing closure, and power-optimization of digital designs.
  • Experience coding within Verilog and/or System Verilog along with scripting languages such as Perl, Tcl, or Python.
  • Hands on experience on Lint/CDC, SDC ownership and qualification, Timing ECO iterations, debugging in mixed-signal simulation environment, etc.
  • Experience in cross interaction with verification, DFT and physical design teams.
  • Understanding of the mixed signal IP flow with modelling and simulation.

About Rambus

With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future.

Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program and gym membership.

  
Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.

 

For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.

 

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