Principal Logic Design - 20396

  • Agoura Hills, United States

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Digital Design Engineer to join our Buffer Chip Design team in Agoura Hills, California. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

 

As a Principal Logic Design Engineer, the candidate will be reporting to the Technical Director, Engineering and is a Full-Time position.

Responsibilities

Design of high-speed CMOS Digital Logic

  • Planning: lead digital designer roles, project managing, design block specification, system level simulation, documentation
  • Implementation: RTL design in Verilog, lint, clock domain crossing (CDC) analysis, top level integration, synthesis, timing analysis, timing closure, DFT-related tasks
  • Verification: work with verification team on planning and execution, simulation, debugging block and system level simulations, formal verification, preparation of technical reviews and product/block documentation
  • Flow and methodology: work in a dynamic and interdisciplinary R&D group that influences and guides Rambus’ technical direction by understanding and contributing to flow and methodology development
  • Interact with technical leaders of the company and senior staff in engineering, marketing, and corporate development to help ensure successful development of high value technologies and products

Qualifications

  • Bachelor's or Master's Degree in Electrical or Computer Engineering
  • 7+ years of relevant digital/ASIC/IC design experience
  • Significant Experience with RTL coding in Verilog and/or VHDL
  • Significant Experience with standard ASIC software tools (synthesis, simulation, equivalence checking, static timing analysis)
  • Strong knowledge of scripting, Linux/Unix environment, and basic C/C++ programming
  • Thorough understanding of ASIC design flow
  • Successful past digital leadership roles
  • Strong design and system knowledge
  • Design for verification experience or understanding (assertion based design strategies, code coverage, functional coverage, test plans etc.) would be an asset
  • Self-starter and fast learner with excellent interpersonal skills
  • Track record of driving technical solutions across organizational boundaries and multiple technical disciplines.
  • Additional knowledge of Analog blocks for behavior modelling and DDR protocols, experience with memory controller, PCIe digital controller, and/or embedded MCU subsystem designs is a plus

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About Rambus

With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future.

Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program and gym membership.
Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may let us know in the application.

For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.

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