Principal Logic Design Engineer - 20373

  • Toronto, Canada

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Logic Design Engineer to join our IP Cores Design team in Toronto, Canada. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

 

As a Principal Logic Design Engineer, the candidate will be reporting to the Senior Principal Engineer, Logic Design and is a Full Time position.

Responsibilities

Digital logic design of high-speed interface IP and sub-systems 

• Planning: lead designer roles, project managing, design block specification, documentation

• Implementation: RTL design in Verilog, lint, clock domain crossing (CDC) analysis, top-level integration, synthesis, timing constraint specification (SDC), timing analysis, timing closure, DFT-related tasks

• Verification: work with verification team on planning and execution, simulation, debugging block and system-level simulations, formal verification (equivalence checking), preparation of technical reviews, and IP/block documentation

• Flow and methodology: work in a dynamic and interdisciplinary R&D group that influences and guides Rambus’ technical direction by understanding and contributing to flow and methodology development

• Interact with the application engineering team to solve issues faced by customers

Qualifications

• Strong expertise in the RTL design and Verilog coding

• Significant experience with ASIC development tools (lint, synthesis, simulation, equivalence checking, static timing analysis)

• Strong knowledge and experience of scripting (Python/Perl/Tcl) and UNIX environment

• Thorough understanding of ASIC design flow

• A high degree of self-motivation and ability to learn fast

• Solid communication and project management skills

• 5+ years of relevant logic design experience

• Bachelor’s or master’s degree in electrical or computer engineering

 

Definite Plus

• Design for verification experience or understanding (assertion-based design strategies, code coverage, functional coverage, test plans, etc.) would be an asset

• Knowledge of electrical interface standards such as PCIe, IEEE Ethernet, and OIF-CEI is an asset

• Silicon debug and troubleshooting skills are desirable

• Experience with embedded processors is an asset

• Experience in IP development is a plus

 

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About Rambus

With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future.

Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, and time-off program.

Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may let us know in the application.

For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.

 

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