SMTS,CAD Engineering

Bangalore | India

Responsibilities

Duties: CDA

  • Responsible for PDK evaluation, setup, customization and flows definition
  • Drive and implement specific Custom Design Automation (CDA) flows such as
    • Schematic entry, Layout design - color aware and DPT/MPT 
    • Parasitic Extraction for transistor level flow
    • Device modelling and Simulation environment in Cadence ADE/ADE-XL/Assembler/Explorer
    • Knowledge and hands-on experience in physical verification – DRC, LVS, DFM checks
    • Knowledge of Deep Submicron Topics such as LFD, PM, MAS, Litho  etc.
    • Knowledge of Electrical verification like IREM (VoltusFi/Totem), RelXpert, ERC, PERC
  • Drive Interfacing between Digital and Analog/Mixed signal methodologies.
  • Develop Custom flows automation, rule deck customizations, improve productivity and efficiency.
  • Train, Deployment and support of CDA to Design teams.
  • Debug flow issues and testcases from Design teams for Simulation, LVS, DRC, IREM, post layout simulation.
  • Responsible for assisting Tapeouts, final chip finishing runs, interface across foundry/customer for rulesets etc.

Qualifications

Skills & Qualification: CDA

  • Good knowledge Analog/Mixed signal Design and Development in Cadence Virtuoso environment.
  • Good knowledge on EDA Tools and Methodologies in Analog/Mixed Signal Design and Development.
  • Good understanding of standards and formats like Spice, CDL, LEF, DEF, Verilog, SPEF, GDS, OA, .LIB, etc.
  • Good knowledge on scripting skills – PERL, TCL, Skill, Ruby, C-Shell scripts etc.
  • Good knowledge on Data management aspects using ICManage / Cliosoft / Perforce / Methodics / SVN etc.
  • Good knowledge of 14nm/10nm/7nm finfet technologies
  • Good knowledge of Deep Submicron Issues / technologies ( < 45 nm technology)
  • Understanding of LSF cluster, Job submission and monitoring is a plus
  • Understanding of tool License features and license administration is a plus

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