SMTS II,Layout

Bangalore | India

Responsibilities

Layout of high-speed analog and digital circuits. Working largely from schematics, the candidate will work with Mixed Signal design engineers to complete the layout of mixed signal circuits and top level connectivity. Responsible for Chip level DRC/LVS/ANTENNA checks and taking the full-chip layout up to mask shop.

Qualifications

  • 8+ years of industry experience in mixed signal CMOS IC layout design at block & chip top level, including chip floor planning and integration
  • Must have proven track record as a lead layout engineer in coordinating and delivering the full chip layouts under tight schedule constraints.
  • Must have experience in handling full chip layout and integration using Cadence Virtuoso ic 6.1 and above
  • Must have implemented and integrated high-speed circuit blocks layouts
  • Experience with Cadence Virtuoso-XL and Mentor Graphics Caliber physical verification tools is a must.
  • Must have good understanding of the analog layout techniques such as device matching, shielding etc.
  • Must be experienced in the layout of ESD devices and I/O circuitry.
  • Must have good working knowledge of Linux operating system.
  • Skills in development of standard and custom analog cell libraries.
  • Experience in DRC, LVS, ERC, Antenna, and post layout extraction.
  • Exposure to foundry DRM, PDK, fabrication & mask process
  • Must have good verbal and written communication skills and experienced in creating documents using Microsoft office
  • Hands on experience on fin-fet process is desirable.
  • Educational qualification: BE or diploma in engineering

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