SMTS II,Signal Integrity Engineering

Sunnyvale | United States

At Rambus, we are turning incredible possibilities into everyday reality by helping to deliver the innovations that greatly impact the world we live in. We create leading-edge semiconductor and IP products, spanning memory and interfaces to security to smart sensors and lighting. Our products are integrated into tens of billions of devices and systems around the globe, running critical applications for Big Data, Internet of Things (IoT), mobile, consumer and media platforms.


And our history runs deep – we have been a staple in Silicon Valley for the past 25 years and are continually anticipating key technology trends and are developing innovations that drive market changes. From a pure IP provider to becoming a fabless chipmaker, Rambus is evolving to address critical challenges in the semiconductor industry.

As a dynamic organization, we are always seeking to hire exceptional talent to join some of the brightest inventors and engineers in the world to explore their passions to develop products that have real life impact. As well, Rambus benefits are among the most comprehensive and competitive in Silicon Valley.



Memory and interfaces are in our DNA. Leveraging over two decades of high-speed circuit design leadership, we make high-performance, low-power memory and serial link interface chips and IP cores to meet the needs of increasingly diverse enterprise and mobile applications. Featuring proven IP and advanced technology, our product families include server DIMM chipsets, R+ DDRn PHYs and R+ Serial Link PHYs.


Rambus is looking for a highly motivated Signal Integrity Engineer working on modeling, analysis, and simulations of signal integrity (SI) and power integrity (PI) of high-speed memory interfaces.


In this highly visible role, the candidate will create SI/PI methodologies and run simulations for the latest memory interfaces for our IP portfolio. These interfaces include the latest GDDR6 16Gig, DDR5 6.4Gig and HBM3.0 (and much more). You will work with our design team to define specifications and system design requirements such are packaging and PCB routings, IC-PKG-BRD decoupling requirements, channel simulations and jitter sensitivity analysis. You will help Rambus’ customers through the implementation of the IP and help application engineers during debug and bring up in lab if needed. You will have the opportunity to work on new memory initiatives, use your creativity to enable the industry for the next generation of IOs and SerDes which will enable the servers, autonomous cars, AI and networking.


  • Electrical Engineering degree with emphasis on electromagnetics (EM), SI, PI, Analog, RF or advanced packaging
  • Prior experience simulating at least two types of memory interfaces is required (i.e. DDR4, DDR5, GDDR5/6, HBM2/3, LPDDR4/5)
  • Solid theoretical background and understanding in EM and transmission line theory is a must
  • Must understand package and PCB design, be able to edit APD/Allegro layout files. Know SI/PI driven BGA assignment methodology and be able to simulate for the trade-offs in the context of a system.
  • Know the mechanisms of crosstalk and jitter in source-synchronous interfaces and be able to include the effect of such losses into low BER simulations  
  • The candidate should be proficient with simulations using Spice and ADS
  • Understanding of equalization techniques such as FIR/DFE/CTLE is needed
  • Experience with commercial EDA tools such as ADS, HFSS, Q3D/PowerSI
  • Familiarity with RedHawk/Totem or XcitePI and Virtuoso is a strong plus
  • Lab characterization experience of passive components, link margin, or noise using realtime and sampling scopes and using VNA/TDR is a big plus  
  • Basic knowledge of circuits used in high-speed link design is preferred.
  • Excellent writing and presentation skills are essential as well as good communication skills to work with customers and cross-functionally


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