Sr Principal Analog Engineer - San Jose, CA #20711

  • Work from Home Location, San Jose, California, United States, 95134
  • 4453 North First Street, Suite 100, Alviso, San Jose, California, United States, 95134

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Sr Principal Analog Design Engineer to join our Bufferchip Design team in San Jose, California. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

 

As a Sr Principal Analog Design Engineer, the candidate will be reporting to the Director of Analog Design Engineering and is a Full-Time position. Successful applicant will have highly visible role in product definition/design across Rambus sites.

 

Location: San Jose, CA with the possibilities of remote work.

 

Responsibilities

  • Define optimal architecture of PLLs and DLLs to achieve competitive product specifications
  • Design PLLs, DLLs and high-sped clock distribution including high-performance and high-speed circuits blocks
  • Create high level model for design tradeoff analysis and behavior model for verification simulations
  • Create floorplan and work with layout team to demonstrate post extraction performance
  • Document analysis and simulation to show that design achieves critical electrical, timing parameters and pre-silicon verification flow
  • Work with the Lab/System team for test plan, silicon bring up and characterization
  • Mentor junior designers

Qualifications

  • MS EE and 5+ years or PhD EE and 7+ years’ experience of CMOS analog/mixed-signal circuit design
  • Prior experience in PLL circuit design with silicon demonstration
  • Good knowledge of design principles for practical design tradeoffs
  • Fundamental knowledge of basic building blocks like bias, VCO, LC-VCO, charge-pump, op-amp and LDO
  • Circuit design experience in DSM process nodes 28nm and below
  • Experience in modeling with matlab, Verilog-A, verilog is desirable
  • Experience in digitally assisted design is desirable
  • Experience in designing memory interfaces such as DDR 4/5 or serial links such as PCIE is desirable
  • Experience working in leading R&D and future technology development projects is desirable
  • The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams
     

About Rambus

 

With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future.

 

Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program and gym membership.

 

Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.

 

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may let us know in the application.

 

For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.

 

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