Sr Member Technical Staff - Layout

Bangalore | India

At Rambus, we are turning incredible possibilities into everyday reality by helping to deliver the innovations that greatly impact the world we live in. We create leading-edge semiconductor and IP products, spanning memory and interfaces to security to smart sensors. Our products are integrated into tens of billions of devices and systems around the globe, running critical applications for Big Data, Internet of Things (IoT), mobile, consumer and media platforms.

 

And our history runs deep – we have been in Silicon Valley for 25+ years and are continually anticipating key technology trends and are developing innovations that drive market changes. From a pure IP provider to becoming a fabless chipmaker, Rambus is evolving to address critical challenges in the semiconductor industry.

 

As a dynamic organization, we are always seeking to hire exceptional talent to join some of the brightest inventors and engineers in the world to explore their passions to develop products that have real life impact. As well, Rambus benefits are among the most comprehensive and competitive in Silicon Valley.

Responsibilities

  • Layout of high-speed analog and digital circuits. Working largely from schematics, the candidate will work with Mixed Signal design engineers to complete the layout of mixed signal circuits and top level connectivity. Responsible for Chip level DRC/LVS/ANTENNA checks and taking the full-chip layout up to mask shop.

Qualifications

  • 6+ years of industry experience in mixed signal CMOS IC layout design at block & chip top level, including chip floor planning and integration
  • Must have proven track record as a lead layout engineer in coordinating and delivering the full chip layouts under tight schedule constraints.
  • Must have experience in handling full chip layout and integration using Cadence Virtuoso ic 6.1 and above
  • Must have implemented and integrated high-speed circuit blocks layouts
  • Experience with Cadence Virtuoso-XL and Mentor Graphics Caliber physical verification tools is a must.
  • Must have good understanding of the analog layout techniques such as device matching, shielding etc.
  • Must be experienced in the layout of ESD devices and I/O circuitry.
  • Must have good working knowledge of Linux operating system.
  • Skills in development of standard and custom analog cell libraries.
  • Experience in DRC, LVS, ERC, Antenna, and post layout extraction.
  • Exposure to foundry DRM, PDK, fabrication & mask process
  • Must have good verbal and written communication skills and experienced in creating documents using Microsoft office
  • Hands on experience on fin-fet process is desirable.
  • Educational qualification: BE or diploma in engineering

Rambus offers a competitive compensation package, which includes a strong base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program and gym membership.

 

Rambus creates cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting. Our chips, customizable IP cores, architecture licenses, tools, services, training and innovations improve the competitive advantage of our customers. We collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation labs. Our products are integrated into tens of billions of devices and systems, powering and securing diverse applications, including Big Data, Internet of Things (IoT), mobile, consumer and media platforms. At Rambus, we are makers of better. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.

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