Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional PE Security Engineering to join our Silicon IP team in San Francisco, CA or San Jose, CA. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. This senior engineer will coordinate our secure software development processes, analyze our current products for security vulnerabilities and compliance with relevant standards, participate in product certification activities, and play a key role in the security design for all of the products we develop in the future.
The successful candidate will demonstrate skills and interest in the theory & practice of secure development, testing, and validation and use those skills to influence our development practices across the business unit. To be successful this person will need to be comfortable accepting responsibility and working with a large team and across multiple disciplines and with teams in several Rambus development sites. A 'can-do' attitude is required for this role along with determination to continually improve our solutions. Your responsibilities will include oversight of our secure software QA process, development of threat models, development of countermeasures, ensure our products are in line with the latest security standards and processes, including certification standards, and identification of the best automated solutions for code analysis and testing.
As a PE Security Engineering, the candidate will be reporting to the Dir Engineering and is a Full-Time position. This engineer will work closely with other ASIC engineers and architects, as well as security, cryptography, verification and software engineers to architect, design, implement, and integrate digital hardware for the CryptoManager Root-of-Trust product, and Crypto Cores line of products, including Post-Quantum cores and those with DPA and FIA countermeasures.
Responsibilities
- Implement (RTL-level in Verilog) hardware IP blocks that are part of Rambus Security’s IP portfolio (Root of Trust, cryptographic cores, etc.)
- Develop side-channel analysis (SCA) and fault injection attack (FIA) countermeasures for symmetric- and public-key (including post-quantum) cryptography hardware cores
- Assist DPA and Fault evaluation
- Research, invent and patent/publish new techniques in the field of SCA countermeasures, fault resistance and efficient hardware designs
- Represent Rambus Security at international workshops and conferences
- Create internal and external documentation
- Assist verification engineers with test plan creation and debugging
- Assist with EDA tool-related tasks, such as synthesis, static-timing analysis, logical equivalency checking, linting, continuous integration, and help improve flows and scripts
Qualifications
Experience and Skills
- MS/PhD degree in electrical or computer engineering required
- 8 plus years working in secure hardware design (a PhD degree with relevant research experience may partially substitute for the work experience requirement)
- Demonstrated proficiency in Verilog and digital design
- Familiarity with front-end ASIC design flows, including design, simulation, synthesis, timing analysis, logical equivalence checking, and linting/rule checking. Experience with back-end flows, especially place-and-route, is beneficial
- Expertise in some or all of the following areas is beneficial:
- Knowledge of HW security architectures and IPs (secure MCU cores, cryptographic co-processors, secure memories, secure elements, smart cards)
- Design and implementation of efficient cryptographic algorithms, including quantum-safe algorithms
- Experience on side-channel and fault attacks and countermeasures
- High performance CPU architecture and design
- Clock and reset domain crossing techniques
- Hardware development experience in UNIX/Linux environments, including supporting tasks such as shell scripting and basic Perl scripts
- Ability to work with technical writers in the production of technical documentation
Tools/Technologies
- Verilog, SystemVerilog, Perl
- Shell scripting, Python, Tcl
- Unix, Linux
- Xilinx Vivado
- Front-end ASIC design tools and simulation
About Rambus
With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future.
Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.
The US salary range for this full-time position is $145,600 to $270,400. Our salary ranges are determined by role, level and location. The successful candidate’s starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.
Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.
Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may let us know in the application.
Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services.
For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.