SMTS Systems Engineering

  • Bangalore, India

We are seeking a highly skilled and motivated Post-Silicon Validation Engineer to join our dynamic team. As a Post-Silicon Validation Engineer your primary focus will be on developing and executing comprehensive validation plans, debugging complex issues, and collaborating closely with cross-functional teams to drive product quality and success.

Responsibilities

  • Collaborate with design and verification teams to define validation plan, strategies, objectives, and requirements for post-silicon validation activities.
  • Develop and implement validation tests, including test benches, test cases, and automation scripts, to validate the functionality and performance of the silicon.
  • Execute validation tests on silicon prototypes and evaluate results to identify and diagnose design defects, functional issues, and performance bottlenecks.
  • Analyze and debug complex issues to identify root causes and work closely with design, architecture, and software teams to propose and implement effective solutions.
  • Continuously improve and maintain the validation infrastructure, including test automation frameworks, tools, and methodologies, to streamline validation processes and increase productivity.
  • Collaborate with cross-functional teams, including design, verification, software, and system teams, to drive product quality, resolve issues, and ensure timely product releases.
  • Prepare comprehensive validation reports, including test plans, test procedures, and defect tracking documentation, to communicate validation progress, results, and recommendations.
  • Stay up-to-date with the latest industry trends, emerging technologies, and best practices in post-silicon validation to enhance your technical expertise and contribute to process improvements.

Qualifications

  • Bachelor's  or Master’s degree in Electrical Engineering, Electronics or a related field. Advanced degree is a plus.
  • 5-8 years of experience in high-speed IO validation and debugging, with preferable knowledge in DDR protocol validation.
  • Solid understanding of semiconductor device architectures, digital logic design, and verification methodologies.
  • Proficiency in programming languages such as C/C++, Python, or scripting languages used in test automation.
  • Hands-on experience with validation tools and methodologies, such as simulation tools, logic analyzers, oscilloscopes, BERT scope and JTAG debuggers.
  • Strong analytical and problem-solving skills with the ability to debug complex hardware and software interactions.
  • Excellent communication and interpersonal skills to collaborate effectively with cross-functional teams.
  • Ability to work independently and multitask in a fast-paced environment with a high attention to detail.

Apply Now

Please send me more jobs like this by email

Not You?

Thank you

People Also Viewed

MTS Verification Engineering

2024-21388 Bangalore India Bangalore, India Engineering
Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead/Senior Design Verification Engineer to join our PCIe Express IP Products team in Bangaluru, India.  The successful candidate will participate in pre-silicon RTL...

MTS CAD Engineering

2023-21171 Bangalore India Bangalore, India Engineering
Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional SMTS CAD Engineer to join our Corporate Ops CAD team in Bangalore, India. Candidates will be joining some of the brightest inventors and engineers in the world to de...

PE Logic Design

2024-21361 Vught Netherlands Boxtelseweg 26A, Vught, Netherlands Engineering
Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead Member of Technical Staff Logic Design Engineer to join our Silicon IP team in Vught part of the Security Business Unit of Rambus. Candidates will be joining so...

Principal Layout Engineer

2024-21442 Shanghai China 1/F, Building 10, No. 696 Weihai Road, Shanghai, China, 000001 Engineering
Rambus, a premier chip and silicon IP provider, is seeking to hire a exceptional Layout Designers  to join the DDR interface team in Johns Creek, GA. Candidates will be joining some of the brightest inventors and engineers in the world to develop ...

Senior Principal ASIC Static Timing Designer

2024-21440 Chapel Hill North Carolina United States 1512 East Franklin St., Suite 200, Chapel Hill, North Carolina, United States, 27514 Engineering
Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Senior Principal Static Timing Design Engineer to join our Memory Interface Design team in Raleigh, North Carolina (remote option available). Candidates will be join...

Principal Verification Engineer-DDR Exp

2023-21117 San Jose California United States Work from Home Location, San Jose, California, United States, 95134. 4453 North First Street, Suite 100, Alviso, San Jose, California, United States, 95134 Engineering
Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Verification Engineer to join our Memory Interconnect Design team in San Jose, California. Candidates will be joining some of the brightest inventors and e...

Job Alerts

Not You?

Thank you

Apply Now

Please send me more jobs like this by email

Not You?

Thank you