Lead MTS Systems Engineering

  • Bangalore, India

We are seeking a highly skilled and motivated Post-Silicon Validation Engineer to join our dynamic team. As a Post-Silicon Validation Engineer your primary focus will be on developing and executing comprehensive validation plans, debugging complex issues, and collaborating closely with cross-functional teams to drive product quality and success.

Responsibilities

  • Collaborate with design and verification teams to define validation plan, strategies, objectives, and requirements for post-silicon validation activities.
  • Develop and implement validation tests, including test benches, test cases, and automation scripts, to validate the functionality and performance of the silicon.
  • Execute validation tests on silicon prototypes and evaluate results to identify and diagnose design defects, functional issues, and performance bottlenecks.
  • Analyze and debug complex issues to identify root causes and work closely with design, architecture, and software teams to propose and implement effective solutions.
  • Continuously improve and maintain the validation infrastructure, including test automation frameworks, tools, and methodologies, to streamline validation processes and increase productivity.
  • Collaborate with cross-functional teams, including design, verification, software, and system teams, to drive product quality, resolve issues, and ensure timely product releases.
  • Prepare comprehensive validation reports, including test plans, test procedures, and defect tracking documentation, to communicate validation progress, results, and recommendations.
  • Stay up-to-date with the latest industry trends, emerging technologies, and best practices in post-silicon validation to enhance your technical expertise and contribute to process improvements.

Qualifications

  • Bachelor's  or Master’s degree in Electrical Engineering, Electronics or a related field. Advanced degree is a plus.
  • 5-8 years of experience in high-speed IO validation and debugging, with preferable knowledge in DDR protocol validation.
  • Solid understanding of semiconductor device architectures, digital logic design, and verification methodologies.
  • Proficiency in programming languages such as C/C++, Python, or scripting languages used in test automation.
  • Hands-on experience with validation tools and methodologies, such as simulation tools, logic analyzers, oscilloscopes, BERT scope and JTAG debuggers.
  • Strong analytical and problem-solving skills with the ability to debug complex hardware and software interactions.
  • Excellent communication and interpersonal skills to collaborate effectively with cross-functional teams.
  • Ability to work independently and multitask in a fast-paced environment with a high attention to detail.

Apply Now

Please send me more jobs like this by email

Not You?

Thank you

People Also Viewed

Intern

2024-21271 Vught Netherlands Boxtelseweg 26A, Vught, Netherlands Engineering
Are you looking for a great opportunity to enrich your university studies?   Rambus, a premier chip and silicon IP provider, is seeking for an Embedded Hardware Design intern to join our team in Vught or Rotterdam as part of the Silicon IP Busines...

Indirect Procurement Manager

2024-21427 San Jose United States 4453 North First Street Suite 100, San Jose, United States, 95134 Supply Chain & Corporate Operations
Rambus, a premier chip and silicon IP provider, is seeking to hire a highly skilled Indirect Procurement Manager to join our team. Candidates will be joining some of the brightest inventors and engineers in the world to enable the development of p...

SMTS Verification Engineering

2024-21351 San Jose California United States 4453 North First Street, Suite 100, Alviso, San Jose, California, United States, 95134 Engineering
Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Verification Engineer to join our Memory Interface Chip team in San Jose. Candidates will be joining some of the brightest inventors and engineers in the w...

Lead MTS Validation Engineering (New Grads also welcome)

2024-21412 San Jose California United States 4453 North First Street, Suite 100, Alviso, San Jose, California, United States, 95134 Engineering
Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead MTS Validation Engineering to join our Memory Interface team in San Jose California. Candidates will be joining some of the brightest inventors and engineers in...

SPE Applications Engineering

2024-21320 San Jose United States 4453 North First Street, Suite 100, San Jose, United States, 95134 Engineering
Seeking an experienced applications engineer with DRAM and failure analysis expertise to support international customers of Rambus DDR4 and DDR5 memory interface chips in Boise, ID.  Analyze and debug complex technical issues involving DRAM, memor...

Job Alerts

Not You?

Thank you

Apply Now

Please send me more jobs like this by email

Not You?

Thank you